When semiconductor devices such as LSIs or the like are connected through transmission lines, impedance matching is important to avoid reflection or the like of the signals. A termination circuit is connected to the transmission line for impedance matching.
There are plural circuit configurations for the termination circuit. Many such configurations include a resistance circuit disposed on at least one of the pull-up side, which is between a transmission line and a power source (the positive side), and the pull-down side, which is between the transmission line and the ground (the negative side of the power source). Thevenin termination includes resistance circuits disposed on both the pull-up side and the pull-down side.
FIG. 1A through FIG. 1C respectively illustrate termination circuits according to first through third conventional examples. In these diagrams, the circuit configurations of only the pull-down side are illustrated. This is because these circuits have basically the same configurations regardless of whether they are disposed on the pull-down side or the pull-up side. By referring to these diagrams, conventional termination circuits will be explained.
In FIG. 1A through FIG. 1C, “digital” represents a digital signal, and “analog” represents an analog signal. “1” represents a node on a transmission line or a signal line connected to that node. Herein, “1” is referred to as a connection node.
The termination circuit illustrated in FIG. 1A has a plurality of N-channel MOS FETs (referred to as “NMOS transistors, hereinafter) 2-0 through 2-n (in the diagram, there are n+1 NMOS transistors). The NMOS transistors 2-0 through 2-n are connected in parallel each other and they are connected to the connection node 1. Resistance values (gate widths) of the NMOS transistors 2-0 through 2-n are different from each other. Resistance value of the termination circuit (referred to as “termination resistance value”, hereinafter) is controlled by selecting one or more of the NMOS transistors 2 using the digital signals [0]-[n]. In FIG. 1A, “[0]” through “[n]” added to “digital” represent correspondence to the NMOS transistors 2-0 through 2-n. 
Other examples of termination circuits that adjust the termination resistance value by selecting MOS transistors with digital signals are described in, for example, Japanese Laid-open Patent Publication No. 2006-332276 and Japanese Laid-open Patent Publication No. 2006-42136.
The resistance value between drain and source of an NMOS transistor varies depending upon the voltage applied to the gate (gate-source voltage). The termination circuit illustrated in FIG. 1B is described, for example, in Japanese Laid-open Patent Publication No. 7-297678. In that termination circuit, a P-channel MOS FET (referred to as “PMOS transistor” hereinafter) 3 and an NMOS transistor 4 are connected in parallel and they are connected to the connection node 1. The termination resistance value is controlled by adjusting the voltages of analog signals “analog” supplied respectively to the gates of the MOS transistors 3 and 4. Note that “analog_n” and “analog_p” represent analog signals to be supplied to the NMOS transistor 3 and PMOS transistor 4, respectively.
In another termination circuit, a PMOS transistor and an NMOS transistor are connected in parallel, and digital signals are supplied to the gate of each MOS transistor instead of analog signals.
The termination circuit illustrated in FIG. 1C is described in, for example, Japanese Laid-open Patent Publication No. 9-261035. That termination circuit has a configuration in which the drain of an NMOS transistor 5 is connected to the connection node 1 and an NMOS transistor 6 is provided between the source of the NMOS transistor 5 and the ground. That is, two NMOS transistors 5 and 6 are cascoded.
In the termination circuit illustrated in FIG. 1C, a digital signal “digital” and an analog signal “analog” are supplied to the NMOS transistor 5 and the NMOS transistor 6, respectively. The termination resistance value is adjusted by the analog signals “analog”.
In a termination circuit, the resistance value between the drain and the source of a MOS transistor varies depending upon a voltage applied to the drain or the source. Thus, the termination resistance value of the termination circuit varies depending upon a voltage applied to the termination circuit. In the termination circuits described above, the voltage applied to the drains of the NMOS transistors 2 in FIG. 1A, the voltage applied to the source and the drain of the PMOS transistor 3 and the NMOS transistor 4 in FIG. 1B, and the voltage applied to the drains of the NMOS transistors 5 and 6 vary due to the voltage at the connection node 1. The variation of the termination resistance value causes impedance mismatching of a transmission line. Thus, the variation of the termination resistance value is desired to be suppressed.
In the termination circuit illustrated in FIG. 1A, i.e., a circuit in which only digital signals are supplied to the gate, it is difficult to suppress variations in the termination resistance value caused by variation in the voltage at the connection node 1. In the termination circuit as illustrated in FIG. 1B or FIG. 10, i.e., a circuit in which analog signals are supplied to the gate, variations in the termination resistance value may be suppressed by adjusting analog signals supplied to the gate. However, this configuration requires a circuit for generating analog signals, making the circuit scale larger. This is undesirable in view of production cost.
In the pull-up side, the voltage between drain and source of a MOS transistor varies similarly depending upon the voltage at the connection node 1. The voltage between drain and source of the MOS transistor also varies depending upon variations in power source voltage (bias voltage). Accordingly, it is important to prevent matching conditions from being deteriorated by variations in the terminal resistance value (total resistance value) regardless of configurations of terminal circuits.